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MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 1 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 features and benefits ? level shifting between micro - controller pwm outputs and 3 external n - fet half - bridges ? 100% pwm operation ? low offset, low drift, fast current sense amplifier ? operating range vsup = [4.5, 28] v , 45v abs. max ? fault interrupt & feedback to microcontroller ? under & overvoltage protection ? overtemperature protection ? vds and vgs external fet monitoring ? sleep mode with low quiescent current ? compatible with 3v and 5v mi cro - controllers ? charge - pump provides nfet r everse polarity drive application examples ? fail - safe applications ? low - t orque control applications ? bldc s ine wave applications (pmsm) ordering information part no. temperature code package code option code comment MLX83202 k ( - 40c to 125c) lq (qfn32, 5x5mm) aaa 000 25 ohm 3hb (*) MLX83202 k pf (tqfp48 , 7x7mm) aaa 000 25 ohm 3hb (*) mlx83203 k lq (qfn32, 5x5mm) aaa 000 8 ohm 3hb mlx83203 k pf (tqfp48 , 7x7mm) aaa 000 8 ohm 3hb (*) (*): derivative s of mlx83203klq aaa - 000 available on high volume request 1 functional dia gram 2 general description the MLX83202/ mlx83 203 family of pre - drivers is designed to drive high - current n - type fet 3 - phase motor control applications. the built - in eeprom allows extensive configurability of the pre - driver without the need for external resistors and spi interface programming. this reduces the p ack age pin count to only 32. all output voltages are moni tored for failure conditions. the microcontroller is informed of the failure condition via a fast serial interface . the device comprises a current shunt amplifier , with a high gain bandwidth (gbw), offe r ing a fast settling time with low noise. this makes the pre - driver s ideal for precise torque control applications like e.g. electrical power ste ering and brake by wire . a combination of bootstrap and charge pump enables driving 6 n fets, with gate charge s up to 400nc /nfet with a minimum of device self - heating . the ic reset level below 4.5v allows for low - voltage operation.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 2 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 table of contents 1 functional diagram ________________________________ ________________________________ ____ 1 2 general description ________________________________ ________________________________ ___ 1 3 glossary of terms ________________________________ ________________________________ _____ 3 4 absolute maximum ratings ________________________________ _____________________________ 3 5 pin definitions and descriptions ________________________________ _________________________ 4 6 electrical specifications ________________________________ ________________________________ 5 7 block diagram and application circuit ________________________________ ___________________ 10 7.1 pinout schematics ________________________________ ________________________________ 12 7.2 ground connections ________________________________ _______________________________ 13 8 description ________________________________ ________________________________ __________ 14 8.1 supply system ________________________________ ________________________________ ___ 14 8.2 sleep mode ________________________________ ________________________________ ______ 14 8.2.1 sleep mo de status overview ________________________________ ______________________ 15 8.3 enable input ________________________________ ________________________________ _____ 16 8.4 protection and diagnostic functions ________________________________ _________________ 16 8.4.1 drain - source voltage monitoring ________________________________ ___________________ 16 8.4.2 programmable dead time ________________________________ _________________________ 16 8.4.3 supply overvoltage shutdown ________________________________ _____________________ 16 8.4.4 regulated supply overvoltage shutdown ________________________________ _____________ 16 8.4.5 undervoltage warnings ________________________________ __________________________ 17 8.4.6 over temperature warning ________________________________ ________________________ 17 8.4.7 eeprom error warning ________________________________ __________________________ 17 8.4.8 icom diagnostics interface ________________________________ _______________________ 17 8.4.9 pre - driver output state summary ________________________________ ___________________ 19 8.5 eeprom programming ________________________________ ____________________________ 20 8.5.1 memory map ________________________________ ________________________________ __ 20 8.5.2 spi communication ________________________________ _____________________________ 21 8.6 current sense amplifier ________________________________ ____________________________ 25 8.7 fet driver implementation ________________________________ _________________________ 27 8.7.1 normal operation ________________________________ _______________________________ 27 8.7.2 fet driver during sleep mode ________________________________ _____________________ 28 8.8 charge pump ________________________________ ________________________________ _____ 28 8.9 100% pwm with bootstrap ________________________________ __________________________ 29 9 standard information regarding manufacturability of melexis products with different soldering processes ________________________________ ________________________________ ____________ 30 10 esd precautions ________________________________ ________________________________ ____ 30 11 package information ________________________________ ________________________________ _ 31 11.1 package data qfn32 (5x5, 32 leads) ________________________________ ________________ 31 11.2 package data tqfp48_ep 7x7 (48 leads, exposed pad ) _______________________________ 32 11.3 package marking ________________________________ ________________________________ 33 12 disclaimer ________________________________ ________________________________ _________ 34
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 3 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 3 glossary of terms ovt overt emperature ov overv oltage uv under voltage por power - on - reset cp charge p ump vdd logic supply (3.3v or 5v) vds drain - source voltage vg s gate - source voltage hv high v oltage (>5v) 4 absolute maximum ratings all voltages are referenced to ground (gnd). positive currents flow into the ic. the absolute maximum ratings given in the table below are limiting values that do not lead to a permanent damage of the device . e xceeding any of these limits may do so. long term exposure to limiting values may affect the reliability of the device. reliable operation of the ic is only specified within the limits shown in operating conditions. parameter symbol conditi on limit unit min max supply voltage vsup , vbatf t < 5 00ms (note 1 ) - 0. 3 45 v permanent (functional) - 0. 3 28 v vdd supply voltage vdd - 0.3 5.5 v voltage on analog lv van_lv - 0. 3 vdd +0. 3 v digital output voltage vout_dig - 0. 3 vdd+0. 3 v digital input voltage vin_dig - 0. 3 vdd+0. 3 v digital input current iin_dig - 10 10 ma input voltage on phasex pins vin_phase - 0.7 45 v maximum latch C up free current at any pin ilatch according jedec jesd78, aec - q100 - 004 - 100 100 ma esd capability of any other pin esd human body model (note 2) - 2 +2 kv storage temperature tstg - 55 150 c junction temperature tj (note 3) - 40 150 (175 under revision) c thermal resistance package rthja in free air on multilayer pcb (jedec 1s2p) 37 k/w rthjc referring to center of exposed pad 10 k/w table 1 . maximum ratings note: 1. only during load dump pulse. 2. equivalent to discharging a 100pf capacitor through a 1.5kohm resistor conform to mil std 883 method 3015.7 3. for applications with tj > 125c: the extended temperature range is only allowed for a limited period of time. the application mission profile has to be agre ed by melexis. some analog parameters may drift out of limits, but chip function ality is guaranteed .
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 4 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 5 pin definitions and descriptions mlx8320x qfn32 mlx8320x tqfp48 name type function 1 4 ibm lv analog input current sensor input (negative input) 2 5 ibp lv analog input current sensor input (positive input) 3 6 isense lv analog output current sensor output 4 7 fetb1 lv digital input pwm input for low - side n - fet1 (active low), miso for spi 5 8 fetb2 lv digital input pwm input for low - side n - fet2 (active low), clk for spi 6 9 fetb3 lv digital input pwm input for low - side n - fet3 (active low), mosi for spi 7 10 icom lv io diagnostic feedback io, !cs for spi 8 11 en lv io enable input 9 14 phase2 hv output motor phase 2: high - side n - fet2 source connection 10 15 gatet2 hv output pwm output to high - side n - fet2 gate 11 16 cp2 hv input supply input (bootstrap) for high - side n - fet2 gate 12 17 phase1 hv output motor phase 1: high - side n - fet1 source connection 13 18 gatet1 hv output pwm output to high - side n - fet1 gate 14 19 cp1 hv input supply (bootstrap) input for high - side nfet1 15 20 phase3 hv output motor phase 3: high - side n - fet3 source connection 16 21 gatet3 hv output pwm output to high - side n - fet3 gate 17 22 cp3 hv input supply (bootstrap) input for high - side nfet3 gate 18 26 vbo ost hv input charge pump generated supply input 19 28 vreg hv output regulated supply for bootstrap capacitors and low - side pre - driver 20 29 gateb2 hv output pwm output to low - side n - fet2 gate 21 30 gateb3 hv output pwm output to low - side n - fet3 gate 22 31 gateb1 hv output pwm output to low - side n - fet1 gate 23 33 dgnd ground driver ground 24 35 cp hv output charge pump driver output to boost vboost 25 38 vsup hv supply input power supply input 26 39 vbatf hv input vbat sense input for 3 high - side n - fets to monitor vds 27 41 agnd ground analog ground 28 43 fett2 lv digital pwm input for high - side n - fet2 29 44 fett1 lv digital pwm input for high - side n - fet1 30 45 fett3 lv digital pwm input for high - side n - fet3 31 47 vdd lv supply input digital io and current sensor amplifier supply. 32 3 vref lv analog input reference voltage input for current sense table 2 . pin definitions and descriptions
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 5 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 6 electrical specifications dc an d ac operating range (unless otherwise specified) ? t a = - 40 o c to 125 o c , ? vsup = [7, 1 8]v ? vdd = 3.3v or 5v parameter symbol test conditions min typ max units battery supply p.1 supply voltage vsup 7 18 v p.2 supply voltage extended range low vsup_erl functional with relaxed specification 4.5 7 v p.2b supply voltage extended range high vsup_erh functional with relaxed specification 18 28 v p.3 quiescent current drawn from vsup issleep vdd=low 30 ua p.4 operating current drawn from vsup isup_int pre - driver operation without charge pump operation ( en_cp=0) and without switching 1 ma p.5 battery o vervoltage threshold high vsup_ovh warning on icom 35 v p.6 battery o vervoltage threshold low vsup_ovl icom released 3 0 v p.7 battery o vervoltage threshold hyst eresis vsup_ovh y 0.4 1 v p.102 battery o vervoltage debounce time vsup_ov_d eb 2 u s p.8 bat tery u ndervoltage threshold low vsup_uvh warning on icom 5 v p.9 ba ttery u ndervoltage threshold high vsup_uvl icom released 6 v p.10 battery undervoltage threshold hysteresis vsup_uvh y 0.2 0.5 v p.103 battery u ndervoltage debounce time vsup_uv_d eb 10 u s p.11 power on reset level vpor reset released on rising edge of vsup, while vdd = high 3 4.5 v power and temperature p.12 overtemperature protection high ovt_h warning on icom 153 166 183 ? c p.13 overtemperature protection low ovt_l icom released 123 137 153 ? c
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 6 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 vdd io supply input p.14 vdd o perating current idd maximum i nput current includes icom current sourcing 20 ma p.15 vdd pull down resistance vddrpd 2 0 0 300 370 kohm p.16 vdd input voltage vdd vdd= 3.3v or 5v l ogic supply 3 5.5 v p.17 vdd undervoltage high 1 vdd_uv_h nfet control activated 2.7 2.8 5 v p.18 vdd undervoltage low vdd_uv_l nfet control d isable d 2.55 2.7 v p.19 vdd undervoltage hyst eres i s vdd_uv_h y 0.07 0.1 0.13 v p.20 vdd sleep voltage high vddsleeph out of sleep 2. 1 2. 7 v p.21 vdd sleep voltage low vddsleepl goto sleep 1.5 2 .05 v p.22 vdd sleep voltage hyst eresis vddsleeph y 0.45 0.58 0.85 v on - chip oscillator p.25 icom pwm frequency fast ficomf 85 100 115 khz p.26 icom pwm frequency slow ficoms 10.6 12.5 14.4 khz oscillator frequency fosc internal oscillator 6.8 8 9.2 mhz p.27 spi start up pulse duration tspi_su en=low, fett1/2/3=low, fetb1/2/3=high 2048/f osc 4096/f osc s charge pump: cpmode=x (silicon diodes bas16, cpump=1uf,cboost=1uf +creg=4.7uf) resistive load from vboost to gnd rboost_leak rt yp at r oom temperature rm in at 150c tj (excl uding rvreg_leak) 6 8 mohm output slew rate 100 v/us charge pump frequency freqcp 170 200 230 khz charge pump: cpmode=0 load current on vreg ireg_cpmode 0 vreg > 11v , en_cp = 1 40 ma output voltage vreg vreg vsup > 8v , i reg < 40ma 11 12 13 v output voltage vreg vreg vsup =[ 7,8]v , ireg <40ma 10 13 v vboost under voltage high vboost_uvh icom released 6.1 7.2 v vboost under voltage low vboost_uvl warning on icom 5.7 6.7 v charge pump: cpmode=1 load current on vreg ireg_cpmode 1 vreg > 11v , en_cp = 1 20 ma reverse polarity nfet gate voltage (vboost - vsup) vgs_rpfet vsup > 7 ireg < 20ma 5 12 13 v output voltage v reg vreg ireg < 20ma 11 12 13 v vboost under voltage high (vboost - vsup) vboost_uvh icom released 6.1 7.2 v vboost under voltage low (vboost - vsup) vboost_uvl warning on icom 5.7 6.7 v vboost over voltage vboost_dis disable and discharge charge pump at vsup_ov 1 the info vdd_uv_x is used to disable the control of the extern al fets
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 7 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 vreg warnings (cpmode=x) internal resistive load from vreg to gnd rvreg_leak rt yp at r oom temperature rm in at 150c tj 0.3 0.4 mohm p.34 vreg over voltage high vreg_ovh warning on icom 14.2 16.5 v p.35 vreg over voltage low vreg_ovl icom released 13.5 15.8 v p.36 vreg over voltage hyst eresis vreg_ovhy 0.65 1 .3 v p.37 vreg under voltage high vreg_uvh icom released 7.2 8.1 v p.38 vreg under voltage low vreg_uvl warning on icom 6.9 7.8 v vbatf internal leakage from vbatf to gnd rvbatf_leak pre - driver is not in sleep mode 20 ua fet gate drivers p.40 driver on resistance 2 r_dr_on 4 8 ohm p.41 r ise time tr cload = 1nf, 20% to 80% 6 7 15 ns p.42 f all time tf cload = 1nf, 80% to 20% 4 7 15 ns p.43 pull - up on resistance low - side pre - driver ron_up - 10ma tj = - 40 - 10ma, tj = 150 2.4 4 7 ohm pull - up on resistance high - side pre - driver 4 8. 5 ohm p.44 pull - down on resistance low - side pre - driver ron_dn 10ma tj = - 40 10ma, tj = 150 1.5 5.7 ohm pul l - down on resistance high - side pre - driver 9.2 ohm p.45 turn - o n gate drive peak current igon vgs=0v - 1 - 1.4 a p.46 tu rn - o ff gate drive peak current igoff vgs=12v 1 1.6 a p.50 propagation delay tpddrv from logic input threshold to 2v vgs drive output at no load 20 100 ns p.51 propagation delay matching tpddrvm transitions at the different phases at no load condition - 20 20 ns p.52 programmable dead time : asynchronous internal de lay between high - side and low - side pre - driver tdead dead_time [ 2:0]=000 001 010 011 100 101 110 111 0 0.5 0.75 1.0 1.5 2.0 3.0 6.0 us p.55 dead time tolerance tdead_tol - 15 15 % p.53b programmable vds monitor voltage vds_ mon vdsmon[2:0]=000 : disabled 001 010 011 100 101 110 111 0.4 0.6 0.85 1.05 1.25 1.5 1.70 0.5 0.75 1.00 1.25 1.50 1.75 2.00 0.6 0.9 1.15 1.45 1.75 2.00 2.3 v 2 the driver on resistance is < 5 ohm at 25 ? c , m ax imum values correspond with 150 ? c
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 8 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 p.54 programmable vds monitor b lanking time: internal delay between gate signal high and enabling the corresponding vds monitor tvds_bl vds_blank_time[1:0] =00 01 10 11 0.59 1.22 2.5 4.9 0.75 1.5 3 6 0.93 1.94 4.12 8.44 us p.56 sleep gate discharge resistor rsgd internal resistance between fet gate - source pins to switch - off fet. vdd = 0v (sleep mode) vgs =0.5v 1 kohm p.57 trickle charge pump current capability itcp vsup>12v, phase2/3 = vsup, cp2/3=phase2/3+6.5v - 35 - 25 ua p.58 vgs undervoltage high vgs_uv h icom released 42 70 %vreg vgs undervoltage low vgs_uv l warning on icom 36 63 %vreg p.60 pwm frequency f_dr_pwm 5 20 100 khz p.61 leakage from cpx to phx rcp_leak typ at r oom temperature min at 150c tj 0.75 1 mohm logic io (fet inputs, en input) p.63 digital input h igh voltage vin_dig_h minimum voltage for input to be treated as logical high 70 % v dd p.64 digital input l ow voltage vin_dig_l maximum voltage for input to be treated as logical low 30 %vdd p.65 input pull - up resistance rin_dig_pu fetb1, fetb2, fetb3 90 410 k ohm p.66 input pull - down resistance rin_dig_pd fett1,fett2, fett3 90 410 kohm p.67 input pull - down resistance r_en_pd en 90 410 kohm spi timing p.68 spi initial setup time tspi_isu 2 us p.69 spi clock frequency fspi 500 khz p.70 rise/fall times tspi_rf clk, csb, miso, mosi 200 ns p.71 csb setup time tcsb_su 1 us p.72 csb high time tcsb_h 2 us p.73 clock high time tclk_h 1 us p.74 clock low time tclk_l 1 us p.75 data in setup time tdi_su 1 us p.76 data in hold time tdi_h 500 us p.77 data out ready delay tdo_r cload at fetb1<50pf 500 us eeprom read delay t_ee_rd ee_rd = 1 6 us eeprom write delay t_ee_wr ee_rd = 1 12 ms icom output p.78 pullup current icom_pu vicom=0v - 2.2 3 - 5 ma p.79 pulldown current icom_pd vicom=vdd 5 2.6 ma enable input p.80 bridge disable propagation delay en_pr_del from bridge enable en < 0.2*vd d to vgs < 0.5v, cload=1nf 1 us
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 9 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 current sense amplifier p.81 input offset voltage vis_io input diff. voltage wit hin +/ - 100mv, common mode [ - 0.5, 1.0 ] v - 7.3 7.6 mv p.82 input offset voltage thermal drift vis_io_tdr ift - 10 10 uv/ ? c p.83 input common mode rejection dc is_cmrr_d c 60 db p.84 input common mode rejection 1mhz is_cmrr_a c 40 db p.85 input power supply rejection dc for vdd supply is_psrr_d c 60 db p.86 input power supply rejection 1mhz for vdd supply is_psrr_a c 40 db p.87 closed loop gain is_gain gain programmable in eeprom - 3% 8.0 10.3 13.3 17.2 22.2 28.7 37.0 47.8 +3% - p.88 output settling time is_set amplified output to 99% of final value after input change 1.0 us p.89 output voltage range high v_isensem ax current sense output max level vdd - 0.020 vdd v p.90 output voltage range low v_isensem in current sense output min level gnd gnd +0.020 v p.91 output short circuit current to ground i_isensesc output current saturation level 1.4 ma p.92 gbw is_gbw 10 mhz p.93 output slew rate is_sr 40 v/us p.94 cm spike recovery is_cm_rec cm spike=+ - 1.5v, duration=250nsec 730 ns p.95 vref voltage input vref 0 50 %vdd table 3 . electrical specifications
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 10 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 7 block diagram and application circuit figure 1 . block diagram
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 11 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 figure 2 . application schematic 1 figure 3 . application schematic 2: internal dead time + hs reverse polarity nfet
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 12 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 7.1 pinout schematics principle schematics highlighting esd connections: figure 4 . pin internal connections
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 13 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 7.2 ground connections figure 5 . ground connections
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 14 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8 description 8.1 supply system figure 6 . supply system, cpmode=0 figure 7 . supply system, cpmode=1 the supply for the ic operation is supplied via vsup and vdd : ? vdd supplies the ios, and the amplifier. o mind when supplying vdd with a limited output impedance (for instance from a microcontroller io ) that the performance of the amplifier may be affected . ? vsup supplies the internal operation and the charge pump. see also chapter: 8.8 charge pump . 8.2 sleep mode sleep mode is activated when the supply input vdd is pulled be low vddsleepl . in sleep mode the current consumption on vsup is reduced to issleep. p in state in sleep mode input/ o utput fettx, fetbx, en, vref, icom input pins, supplied from vdd. gnd isense supplied from vdd gnd vreg supply regulator is disabled gnd vboost, hsd externally connected to supply ~vbat cp charge pump is disabled gnd cpx any charge that remains after vreg is disabled will leak to ground gnd gatetx phasex vsup>4.5v in sleep mode gate - discharge - resistors (rsgd) between gatetx and phasex are activated (see chapter 8.7.2 fet driver during s leep mode ) gnd gatebx vsup>4.5v in sleep mode gate - discharge - resistors (rsgd) between gatebx and dgnd are activated. (see chapter 8.7.2 fet driver during s leep mode ) gnd table 4 . state of ic during sleep mode
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 15 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 note : ? in case input pins are externally pulled high while vdd low, current will flow into vdd via internal esd protection diodes . this condition is not allowed. ? when vdd is pulled low, also icom will go low. this should not be inter p reted as a diagnostic interrupt . 8.2.1 sleep mode status overview name type state in sleep mode ibm lv analog input gnd ibp lv analog input gnd isense lv analog output gnd (tied to vdd) fetb1 lv digital input gnd (tied to vdd) fetb2 lv digital input gnd (tied to vdd) fetb3 lv digital input gnd (tied to vdd) icom lv io gnd (tied to vdd) en lv io gnd (tied to vdd) phase2 hv output connected via diode to gate2 gatet2 hv output internal pull down (rsgd) to gnd cp2 hv input any present charge leaks to gnd phase1 hv output connected via diode to gate1 gatet1 hv output internal pull down (rsgd) to gnd cp1 hv input any present charge leaks to gnd phase3 hv output connected via diode to gate3 gatet3 hv output internal pull down (rsgd) to gnd cp3 hv input any present charge leaks to gnd vboost hv input connected via cp diodes to vbat vreg hv output gnd gateb2 hv output internal pull down (rsgd) to gnd gateb3 hv output internal pull down (rsgd) to gnd gateb1 hv output internal pull down (rsgd) to gnd dgnd ground driver ground cp hv output gnd vsup hv supply input power supply input vbatf hv input connected to supply agnd ground analog ground fett2 lv digital gnd (tied to vdd) fett1 lv digital gnd (tied to vdd) fett3 lv digital gnd (tied to vdd) vdd lv supply input externally pulled low vref lv analog input gnd table 5 . pin definitions and descriptions
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 16 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.3 e n able input pulling the enable input (en) low forces the pre - driver to pull all fet gate voltages to ground, switching off al l external transistors ( high impedan ce ) . while en is low , the programming of the eeprom via spi can be initiated by pulling icom low for a time tspi _su . 8.4 protection and diagnostic functions 8.4.1 drain - source voltage monitoring the mlx832 0x provides a drain - source voltage monitoring feature for each external fet to protect against short circuits. this drain - source voltage monitoring comparator can be enabled/disabled in eeprom. the drain - source voltage monitor for a certain external fet i s only active when the corresponding input is set to on and the dead time is over. an additional blanking time can be programmed in eeprom. if the drain - source voltage stays higher than the vds monitor threshold voltage, the vds error is raised. this thr eshold voltage is configurable in eeprom. the reaction of the pre - driver on a vds error can be configured in eeprom with the b ridge f eedback bit. if this bit is set the pre - driver will automatically disable the drivers when a vds error is detected. if not set the pre - driver remains active. in any case the vds error will be reported. vds_comp_en vds_bf_en pre - driver reaction on error event 0 x any drain - source over voltage event is ignored and no error is reported on icom. 1 0 vds_err is reported on icom, but the pre - driver remains active. 1 1 vds_err is reported on icom and the pre - driver is disabled. table 6 . pre - driver reaction on vds error 8.4.2 programmable dead time the pre - drivers internal implementation guarantees that low side and high side of the same external half bridge can not be on at the same time connecting supply directly to ground. see figure 12 for th is internal implementat ion of the pre - driver. the pre - driver also provides a programmable dead time in eeprom. 8.4.3 supply overvoltage shutdown the pre - driver has an integrated vsup over voltage shut down to prevent destruction of the pre - driver at high supply voltages. a vsup_ov event will always switch off the pre - driver, t his reaction can not be masked. 8.4.4 regulated supply overvoltage shutdown the pre - driver has an integrated vreg over voltage shut down. the reaction of the pre - driver on this vreg_ov depends on the status of the b ridge f eedback bit in eeprom. if this vreg_ov_bf_en bit is set the pre - driver will pull all gate voltages low, switching off all external fets.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 17 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 vreg_ov_bf_en pre - driver reaction on error event 0 vreg_ov is reported on icom, but the pre - driver remains ac tive. 1 vreg_ov is reported on icom and the pre - driver is disabled. table 7 . pre - driver reaction on vreg_ov 8.4.5 undervoltage warnings comparators are implemented to detect an under voltage on vsup, vboost, vreg, vdd and vgs. if an under voltage is detected, it will be reported to the mcu. it is the responsibility of the user to take action to assure functional operation. 8.4.6 over temperatur e warning if the junction temperature exceeds the specified threshold, a warning will be communicated to the mcu. the pre - driver will continue in normal operation . it is the responsibility of the user to protect the ic against over temperature destruction. 8.4.7 eeprom error warning to ensure reliable communication with eeprom the pre - driver provides an automatic single bit error correction. if two bits in the addressed word are bad the eeprom gives the eep_err warning, indicating a double error was detected. 8.4.8 ico m diagnostics interface icom is a serial interface that feeds back detailed dia gnostics information to the mcu over a single wire. in normal operation, when no error is detected, icom is high. when an error is detected the pre - driver will inform the mcu vi a a pwm duty cycle on icom. it is the responsibility of the mcu to catch the icom duty cycle and disable the driver if necessary, by pulling en low. each error corresponds to a duty cycle with a 5 bit resolution. the duty cycle is transmitted until the mcu acknowledges the reception of the duty cycle. for the mcu to acknowledge the error, it should be able to keep the line low while icom is pulling t he line high, for a period t ack > t icom . at each icom falling edge the pre - driver checks the actual voltage on icom to detect an acknowledgement. when an acknowledgement is detected the pwm duty cycle is changed to the corresponding duty cycle of the next error to be transmitted. figure 8 . icom diagnostics interface
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 18 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 this sequence of capturing duty cycle and acknowledging continues until all error duty cycles are communicated and the end of frame (eof) duty cycle is being transm itted. by acknowledging this eof all error latches are reset and the icom line goes high again, until a new error is detected. figure 9 . icom serial interface for diagnostics information over a single wire in case multiple errors occur at the same time, priority is defined: 0 is the highest priority and 16 is the lowest priority. see table 8 for an overview of all error conditions that are monitored, the corresponding pwm duty cycle and the priority. priority input error code % d uty cycle debounce time description 16 icom_eof 93.5 n/a end of frame 9 eep_err 55 .0 n/a eeprom ded error 8 vdd_uv 49.5 8us vdd under voltage 7 vsup_ov 44 .0 2us vsup over voltage 6 vsup_uv 38.5 8us vsup under voltage 5 ovt 33 .0 2us ovt (over temperature) 4 vreg_uv 27.5 16us vreg under voltage 3 vgs_uv 22 .0 2us vgs under voltage this event can be masked by setting vgs_uv_comp_en=0 2 vboost_uv 16.5 16us vboost under voltage 1 vreg_ov 11 .0 2us voltage regulator over voltage this event can be masked by setting vreg_ov_bf_en=0 0 vds_err 5.5 2us vds error =vds_t1 || vds_t2 || vds_t3 || vds_b1 || vds_b2 || vds_b3 can be masked by vds_comp_en to avoid erronous triggering due to switching there is a programmable blanking time on top of the debounce time: vds_blanktime[1:0]. table 8 . overview diagnostic errors over icom ( 1 ) : m c u p u l l s i c o m l o w ( 2 ) : m l x 8 3 2 0 x d e t e c t s a c k n o w l e d g e o n f a l l i n g e d g e ( 3 ) : m c u r e l e a s e s i c o m l i n e e r r o r 1 e r r o r 2 e r r o r 3 e o f t a c k t a c k t a c k t a c k ( 1 ) ( 1 ) ( 1 ) ( 1 ) ( 3 ) ( 3 ) ( 3 ) ( 3 ) ( 2 ) ( 2 ) ( 2 ) ( 2 ) t t t t t t t t t t t t t t i c o m
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 19 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 two modes for supplying diagnostic feedback to the mcu are possible and can be set in eeprom. the first mode is the slow response diagnostic mode and uses a larger pwm period to communicate diagnostics information to the mcu over icom. the second mode is the fast response diagnostic mode and uses a pwm period that is ~8 times smaller. this fast mode allows the fastest response time of the interrupt routine form the external mc, but also imp lies the mcu needs to be fast enough in order to be able to capture the duty cycle. for the fast response diagnostic mode the mcu clock needs to be minimum 20mhz. note: ? the different diagnostic feedback modes (slow/fast) are applicable independent of the configuration of the internal hardware protection features. ? when vdd is pulled low to put the pre - driver in sleep mode icom will go low as well. as soon as vdd goes high, icom will go high as well and remains high. no eof may be required. ? at por it is p ossible that the voltages on vsup, vboost and vreg have not been achieved (dut to charging of the external capacitors) and thus it is possible icom may immediately go in diagnostic mode. this implies the mcu has to acknowledge these errors until the under voltage conditions have been resolved. as soon as the eof duty cycle is acknowledged and icom remains high, the pre - driver is ready for normal operation. 8.4.9 pre - driver output state summary below table shows all conditions due to which the pre - driver may be disabled: the pre - driver i s disabled ( high - impedance state ) the pre - driver i s released again as soon as an error condition appears for which the hardware protection is activated ? vsup_ov ? vds ? vreg_ov as soon as the eof has been acknowledged. as soon as vdd = low as soon as vdd = high as soon as en = low as soon as en = high table 9 . pre - driver output summary
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 20 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.5 eeprom programming ? the eeprom data can be programmed during customer production testing by using a ptc - 04, or by the microcontroller via an spi interface. the pre - driver is programmed with default settings per table below. ? the eeprom features single error correction and double error detection. ? note: spi_address[6] == spi_address[7] == spi_address[5] 8.5.1 m emory map spi address[2:0] ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 0 res . res . res . res . res . res. res . res . 1 res . res . res. res. res . res . res . res . 2 dead_time[2:0] vdsmon[2:0] cpmode res. 3 vds_blank_time[1:0] pwm_speed res. cur_gain[2:0]. res. 4 vreg_ov _bf_en vds_ bf_en vds_ comp_en vgs_uv_c omp_en en_tcp en_cp res. res. 5 spi_en 1 res. res. res. res. res. res. table 10 . memory map eeprom bit name description default driver configuration dead_time[2:0] defines the dead time between the hs fet and ls fet of the same phase 011 vdsmon[2:0] defines the detection threshold level of the vds monitoring 111 vds_blank_time[1:0] defines the duration of the vds monitor blanking time after the on - transition of the fet 10 cur_gain[2:0] defines the gain of the current sense amplifier 011 cpmode 1: vboost voltage is regulated relative to vsup. 0: vboost voltage is regulated relative to ground 0 ic configuration spi_en when set, the spi block is enabled. when reset, no spi possible. (in spi mode this value can only be programmed from 1 to 0 , not from 0 to 1 ) 1 vreg_ov_bf_en vreg over voltage bridge feedback enable 1: when vreg_ov=1 ? bridge driver is set in tri - state 0: when vreg_ov=1 ? n o effect on bridge driver . 1 vds_bf_en vds bridge feedback enable 1: when vds_err=1 ? bridge driver is set in tri - state 0: when vds_err=1 ? n o effect on bridge driver . 1 vds_comp_en 1: vds comparator enabled 0: vds comparator disabled 1 vgs_uv_comp_en 1: vgs_uv comparator enabled 0: vgs_uv comparator disabled 1 pwm_speed 1: pwm = ficomf 0: pwm = ficoms 0 en_cp 1: enables boost charge pump 0: disables boost charge pump 1 en_tcp 1: enables trickle charge pump 0: disables trickle charge pump 0 out_reserve_rg undefined 0 table 11 . eeprom bits
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 21 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.5.2 spi communication when the chip is in spi mode the eeprom is programmable and readable via the spi port. 8.5.2.1 entering / e xiting spi mode the mlx83203 will enter from normal mode into spi mode when all below conditi ons are present: ? en = 0 ? all fettx = low and all fetbx high (all fet inputs are disabled) ? icom: o any pending errors have been acknowledged o a low level pulse is applied on icom between 256us ( 2048/fosc ) and 512us ( 4096 /fosc ) the chip will return from spi mode to normal mode when ? en = 1. this means that ? any ongoing eeprom writes will be completed ? the eeprom state machine will copy all eeprom contents into registers during this time the icom pin will be kept low. similar to w hen the mlx83203 comes out of por, after leaving spi mode and returning to normal mode, the mlx83203 will be blocked until the data have been copied to the registers . this assures that all chip parameters are set correctly before starting . note: i t only makes sense for the mcu to call for spi if all errors are clear and acknowledged. 8.5.2.1 spi protocol figure 10 . spi waveform example for read and write (lsb first)
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 22 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 the 16 bit miso/mosi shift registers are controlled via 4 pins which are shared with other functions: p in spi signal comment fetb1 miso the signal on the miso output is guaranteed to be stable while clk is low fetb2 clk clock input fetb3 mosi the mosi shift register is reading in data on the rising edge of clk icom_in csb frames are defined by csb low and have to consist of 16 clock pulses on clk. on the rising edge of csb: ? if comm_err=0 the read/write action is started as requested in the previous frame. ? else (comm_err = miso[14]=1) : a communication error is de tected. n o action will occur (ee_ready latch will remain 0) . this can be: ? either due to a p arity bit failure: mosi[15] in frame n was incorrect. ? or because less or more then 16 rising edges were received during csb low of frame n csb has to r emain high until the read (t_ee_rd ) / write (t_ee_wr ) action is completed. in this case ee_ready= miso[13] bit in the next frame will be h igh else if csb goes low before the requested action is completed ? ee_ready = miso[13] bit in the next frame will be l ow . table 12 . spi signals
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 23 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.5.2.2 spi registers figure 11 . spi registers and relation to internal data latches mosi bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] mosi_data [3 : 0 ] x address [2:0] bit[15] bit[14] bit[13] bit[12] bit[11] bit[10] bit[9] bit[8] mosi_ parity x x cmd [1:0] 00: ee_rd 01: ee_wr 10: ee_ rd aw1 11: ee_ rd aw2 mosi_data [6:4 ] miso bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] miso _data [3:0] (*) x the content from previous mosi[2:0] bit[15] bit[14] bit[13] bit[12] bit[11] bit[10] bit[9] bit[8] miso_ p arity com m _err ee_ready the content from previous mosi[12:11] miso_data [6:4] (*) table 13 . spi registers description (*) miso _data [ 10 :4 ] c omment if mosi (n)[11:12] = ee_wr (w r ite command) then miso(n+1)[10:4] = mosi (n) [10:4] from previous wr instruction the data received via mosi have been shifted into the miso register. this allows the mcu to verify the correct data have been transmitted. in order t o verify if the data have been correct stored into the eeprom, a dedicated r ead command is required. else ; mosi(n)[11:12] <> ee_wr miso(n+1)[10:4] = eeprom(address=mosi(n)[2:0]) in case a read command is received, t he data in the miso register have been copied out of the designated address in the eeprom. mind that 3 read consecutive r ead commands have to be successful to ensure retention time.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 24 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.5.2.3 bit definition b it c omment miso_par mosi_par odd parity of the actual data. so respectively the odd parity of the actual mosi data, or the odd parity of the actual miso data. ee_ready 0 : ee_wr or ee_rd command were not completed when the new frame was started ( on the falling edge of csb) 1 : no ee_wr or ee_rd activity ongoing on falling edge of csb com m _err 1 : communication error occurred during the previous m osi message . possible errors: ? parity bit failure ? less or more the 16 rising edges received during cs b low 0: previous dataframe was received ok: n o communication error cmd [1:0] ee_rd, ee_rdaw1, ee_rdaw2 : 1. a mosi frame is sent with command: mosi[12:11] = ee_rd (below is also applicable for ee_rdawx). 2. csb is kept high long enough (> t_ee_rd ) to ensure the read command can be completed. (else ee_ready will be 0 in next miso frame ) 3. the requested data will be transmitted in the next miso frame. 4. the data in this frame is valid in case a. comm_err = 0 (there was no comm. error during the previous mosi frame) b. ee_ready =1 (the read command was completed on the falling edge of csb) c. miso [15] has the correct parity. ee_wr 1. a mosi frame n is sent with mosi[12:11] = ee_wr. 2. csb is kept high long enough (> t_ee_wr ) to ensure the wr ite command can be completed. (else ee_ready will be 0 in next miso frame) 3. the received data are used in the next miso frame as a first verification step in a total of 3 steps need to verify if the ee_wr was successful. a. verification of the n+1 miso frame . t he n+1 miso frame should have . i. comm_err = 0 (there was no comm. error during the previous mosi frame) ii. ee_ready =1 (the ee_wr command was completed on the falling edge of csb) iii. miso[15] has the correct parity. iv. miso_data(n+1) = mosi_data(n) b. verification step2: ee_rdaw1: the n +1 mosi frame should have cmd = ee_rdaw1 then the n+2 miso frame should have. i. comm_err = 0 (there was no comm. error during the previous mosi frame) ii. ee_ready =1 (the ee_wr command was completed on the falling edge of csb) iii. miso[ 15] has the correct parity. iv. miso_data(n+2) = mosi_data(n) c. verification step3: ee_rdaw2: the n+2 mosi frame should have cmd = ee_rdaw2 then the n+3 miso frame should have. i. comm_err = 0 (there was no comm. error during the previous mosi frame) ii. ee_ready =1 (the ee_wr command was completed on the falling edge of csb) iii. miso[15] has the correct parity. iv. miso_data(n+3) = mosi_data(n) conclusion: in total 3 mosi frames should be generated to ensure successful writing of data.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 25 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.6 current s ense amplifier the sense amplifier offers low input offset, and fast settling times . its input range can be adjusted by applying a suitable voltage on the vref pin , ty pically as a resistor divider from vdd to gnd . f or the definition of vref, the input offset, the current ra nge, and the linear output range of the isense pin should all be taken into account. for input signal: vin = visp - visn, m ax input offset: voffset max = vis_io max + trange * vis_io_tdrift (over full temperature range =trange) visense = (vin +/ - voffset)* is_ gain + vref has to be in the range [v_isensemin, v_isensemax] ? imin = [ ( visensemin C vref) / is_gain + voffset ] / rshunt ? imax = [ ( visensemax C vref) / is_gain - voffset ] / rshunt input offset voltage vis_io input offset voltage thermal drift vis_io_tdrift closed loop gain is_gain isense output voltage range high v_isensemax isense output voltage range low v_isensemin the below table shows the current input range (amp) for two resistive divider settings on vref: 1) vref = vdd/2 for a symmetrical input range 2) vref = vdd/18 for a maximum current level, whil e ensuring it is possible to measure the input offset before starting the motor (isense_min > 0a). remark: for ease of calculation a max temperature offset drift of 1mv was added to the 5mv offset => max input offset = 6mv vdd 3.3 3.3 3(**) 3(**) 5 5 4.5(**) 4.5(**) visensemin 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 visensemax 3.28 3.28 2.98 2.98 4.98 4.98 4.48 4.48 div 2 18 2 18 2 18 2 18 vref 1.65 0.18 1.50 0.17 2.50 0.28 2.25 0.25
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 26 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 voffset 0.006 isense min . 1 mohm gain div2 div18 div2 div18 div2 div18 div2 div18 8 - 198 - 14.4 - 179 - 12 - 304 - 26.2 - 273 - 23 10.3 - 152 - 9.9 - 138 - 8 - 235 - 19.0 - 211 - 16 13.3 - 117 - 6.3 - 105 - 5 - 180 - 13.4 - 162 - 11 17.2 - 89 - 3.5 - 80 - 3 - 138 - 9.0 - 124 - 7 22.2 - 67 - 1.4 - 61 - 0.6 - 106 - 5.6 - 94 - 4 28.7 - 51 0.3(*) - 46 0.9(*) - 80 - 3.0 - 72 - 2 37.0 - 38 1.6 (*) - 34 2.0 (*) - 61 - 1.0 - 54 0 47.8 - 28 2.6 (*) - 25 3 (*) - 46 0.6 - 41 1 isense max . gain div2 div18 div2 div18 div2 div18 div2 div18 8 198 381 179 346 304 582 273 523 10.3 152 295 138 267 235 451 211 405 13.3 117 227 105 206 180 348 162 312 17.2 89 174 80 158 138 267 124 240 22.2 67 133 61 121 106 206 94 185 28.7 51 102 46 92 80 158 72 141 37.0 38 78 34 70 61 121 54 108 47.8 28 59 25 53 46 92 41 82 table 14 . sense amplifier current ranges in amp . examples for 1mohm shunt note : ? (*) applying a gain of 28.7 or higher with div 18 for 3.3v does not allow the measure the input offset ? (**) example s taking a 10% supply variation into account.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 27 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.7 fet driver implementation 8.7.1 normal operation the top side fet drivers are bootstrapped drivers. each of the 6 external fet transistors can be controlled directly via the 6 digital inputs. the 6 external fet transistors (or 3 half bridges) can also be controlled with only 3 digital input signals. this can be done by connecting the fetti to vdd and control the 3 phases via the fetbi inputs . in this mode the mlx 83203 will automatically generate the programmed dead times. figure 12 shows the internal implementation of the driver stage from input to output. the drain source voltage vds as well as the gate voltage vgs are monitored to ensure fail safe operation. the fet gate outputs are all pulled low by pulling en low. figure 12 . i nternal implementation of the driver stage
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 28 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.7.2 fet driver during s leep mode whe n the mlx83203 is in sleep mode a gate discharge resistance (rsgd ~1kohm ) is activated which ensure s the fet gates remain fully in off state. note that is the responsibility of the microcontroller to ensure all gate voltages are low, for instance by setting the en input low, prior to switching to sleep mode. figure 13 . s tate of pre - driver in sleep mode figure 13 phasex is kept low with gatetx through the internal body diode of the pre - driver . 8.8 charge pump eeprom configuration bits default cpmode 1: vboost voltage is regulated relative to vsup. 0: vboost voltage is regulated relative to ground 0 en_cp 1: enables boost charge pump 0: disables boost charge pump 1 table 15 . cp configuration in eeprom standard operation of the charge pump (cpmode=0) is to ensure sufficient gate voltage to the bootstrap capacitors in case of low battery voltage conditions. in this case vboost is regulated compared to gnd level. the charge pump will not be switching when vsup > vreg + 2* vf, with vf= forward voltage of the charge pump diodes . alternatively (cpmode=1) the charge pump can regulate vboost compared to vsup. in this case the cboost cap should be connected to vsup to ensure any supply variations are coupled to the vboost level. in this case vboost can be applied to drive a high side reverse polarity nfet. the disadvantage is an additional amount of dissipation inside the driver to r egulate vreg.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 29 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 8.9 100% pwm with bootstrap a current is drawn from the cp bootstrap pin to the phase pins. this current will discharge the gate voltage on top of any external pull down gate resistance. the below tables show some calculation examples. bootstra p 330 nf bootstrap 100 nf vreg 12 v vreg 12 v qbootstr 3960 nc qbootstr 1200 nc qfet 200 nc qfet 120 nc vgs_initial 11.4 v vgs_initial 10.9 v rcp_leak 0.75 mohm leakage 15 ua leakage 15 ua on time 60 ms on time 10 ms qleak 914 nc qleak 152 nc vgs_end 9.4 v vgs_end 9.8 v vgs drop 2.06 v vgs drop 1.13 v this gate leakage will limit the maximum state time during which 100% pwm can be applied.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 30 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 9 standard information regarding manufacturability of melexis products with different soldering processes our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level according to following test methods: refl ow soldering smds ( s urface m ount d evices) ? ipc/jedec j - std - 020 moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices (classification reflow profiles according to table 5 - 2) ? eia/jedec jesd22 - a113 preconditioning of nonhermetic surface mount devices prior to reliability testing (reflow profiles according to table 2) wave soldering smds ( s urface m ount d evices) and thds ( t hrough h ole d evices) ? en60749 - 20 resistance of plastic - encapsulated smds to combined effect o f moisture and soldering heat ? eia/jedec jesd22 - b106 and en60749 - 15 resistance to soldering temperature for through - hole mounted devices solderability smds ( s urface m ount d evices) and thds ( t hrough h ole d evices) ? eia/jedec jesd22 - b102 and en60749 - 21 solderability for all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with melex is. the application of wave soldering for smds is allowed only after consulting melexis regarding assurance of adhesive strength between device and board. melexis is contributing to global environmental conservation by promoting lead free solutions. for more information on qualifications of rohs compliant products (rohs = european directive on the restriction of the use of certain hazardous substances) please visit the quality page on our website: http://www.melexis.com/quality.asp 10 e sd precautions electronic semiconductor products are sensitive to electro static discharge (esd). always observe electro static discharge control procedures whenever handling semiconductor products.
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 31 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 11 package information 11.1 package data qfn32 (5x5, 32 leads) a a1 a3 b d/e d2/e2 e k l n min 0.80 0.00 0.20 ref 0.18 5.00 b.s.c 3. 5 0 0.50 b.s.c 0.2 0.3 32 max 1.00 0.05 0.30 3. 7 0 - 0.5 table 16 . mechanical dimensions qfn32 5x5, all dimensions in mm [1] general tolerance of d and e is +/ - 0.1mm [2] bottom pin 1 identification may vary depending on supplier figure 14 . package qfn32
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 32 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 11.2 package data tqfp48_ep 7x7 (48 leads, exposed pad) a a1 a2 d/e d1/e1 d2/e2 e l n b c ? ? o max 1.20 0.15 1.05 0.75 0.27 0.20 7 o table 17 . mechanical dimensions tqfp48_ep 7x7, all dimensions in mm figure 15 . package tqfp48_ep
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 33 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 11.3 package marking product name: mlx8320x x = 2 or 3 date code: yyww year and week lot number zzzzzzzz format free top view of the package 8 3 2 0 x y y w w z z z z z z z z
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 34 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 12 disclaimer devices sold by melexis are covered by the warranty and patent indemnification provisions appearing in its term of sale. melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the de scribed devices from patent infringement. melexis reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with melexis for current information . this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life - support or life - sustaining equipme nt are specifically not recommended without additional processing by melexis for each application. the information furnished by melexis is believed to be correct and accurate. however, melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performa nce or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of melexis rendering of technical or other services. ? melexis nv. all rights reserved. for the latest version of this document, go to our website at www.melexis.com or for additional information contact melexis direct: europe, africa, asia: america : phone: +32 1367 0495 phone: +1 603 223 2362 e - mail: sales_europe@melexis.com e - mail: sales_usa@melexis.com iso /ts 16949 and iso14001 certified
MLX83202/mlx83203 automotive nfet pre - drivers 3901083203 page 35 of 35 prelim. data sheet rev 2. 2 4 dec 201 3 13 history of changes r evision a uthor d ate description 1.1 dlm 1 - 3 - 12 ? ee_rd meaning in spi description corrected ? rdson specification split up in on/off ? added rdson for 83202 variant ? added package marking 1.2 dlm 28 - 3 - 12 tqfp48 pin out included 1. 3 dlm 15 - 5 - 12 ? added appl. schematics, pin internal structures, updated block diagram ? updated spi enabling. ? updated icom duty cycles ? updated sleep mode ? updated leakage spec on vbatf max voltage on all pins 1.4 dlm 3 - 7 - 12 final package dimensions. 1.5 rrr 28 - 11 - 12 ? parameters updated per test data . ? device description updated 1.6 soe 21 - 12 - 12 ? information about dc variant of pre - driver moved to separate datasheet 1.7 soe 15 - 01 - 13 ? protection and diagnostic functions updated ? trickle charge pump included 2.0 soe 26 - 02 - 13 2.1 soe 06 - 05 - 13 max voltage on phase pins updated 2.1 soe 04 - 12 - 13 entering spi mode by disabling all 6x fet input signals

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